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<H1>WARTS<BR> Wisconsin Architectural Research Tool Set</H1>

Mark D. Hill, James R. Larus, Alvin R. Lebeck, Madhusudhan Talluri,
and David A. Wood<BR>
<P>
Computer Sciences Department<BR>
University of Wisconsin<BR>
1210 West Dayton St.<BR>
Madison, WI 53706<BR>
warts@cs.wisc.edu<BR>

<P> Wisconsin Architectural Research Tool Set (WARTS) is a collection of
tools for profiling and tracing programs and analyzing program
traces. WARTS currently contains:

<UL>
<LI> <!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~larus/qpt.html">QPT and QPT2</A>, Program profiling and tracing system.
<LI> <!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><A HREF="#CPROF">CPROF</A>,  Cache performance profiler.
<LI> <!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><A HREF="#Tycho">Tycho and dineroIII</A>, Cache simulators.
<LI> <!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><A HREF="http://www.cs.wisc.edu/~larus/eel.html">EEL</A>, Library for editing executable files.
<LI> <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><A HREF="http://www.cs.duke.edu/~alvy/fast-cache">Fast Cache</A>, Framework for memory system simulators.
</UL>

<P> 
WARTS is distributed with the full source and a small amount of
documentation. The tools in WARTS are copyrighted and distributed under
license. A copy of the license is available on ftp.cs.wisc.edu in:
<!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><A HREF="ftp://ftp.cs.wisc.edu/pub/warts/license.ps">~ftp/pub/warts/license.ps</A>
or it can be obtained by writing to the address above.  WARTS is
available without charge for university researchers and is available
to other researchers for a modest research donation.  Contact
warts@cs.wisc.edu for more details.

<P>
We also maintain a list of <!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><A HREF="http://www.cs.wisc.edu/~larus/external_warts.html">changes and improvements to WARTS programs.</A>

<P>
<H2> <A NAME="CPROF">CPROF:</A> </H2>
The CPROF system is a cache performance profiler written by Alvin
R. Lebeck and David A. Wood that annotates source listings to identify the
source lines and data structures that cause frequent cache misses. The
CPROF system consists of two programs: Cprof, a uniprocessor cache
simulator, and Xcprof, an X windows user interface. Cprof processes
program traces generated by QPT (see above) and annotates source lines and
data structures with the appropriate cache miss statistics. Xcprof
provides a generalized X windows interface for easy viewing of annotated
source files.
<P>
The performance of current RISC processors is very sensitive to cache miss
ratios. Programmers, compiler writers, and language designers must
explicitly consider cache behavior to fully exploit a program's
performance potential. CPROF provides detailed information about a
program's cache behavior through full cache simulation. By annotating
lines of source code and data structures with the corresponding number of
cache misses, CPROF helps the user focus on problematic data structures
and algorithms. CPROF aids the programmer in identifying types of
transformations that can improve program cache behavior by classifying
cache misses as: compulsory, capacity, or conflict.
<P>
Note: This product contains software developed by the University of
California, Berkeley and its contributors.
<P>
Our experience using CPROF to tune this subset of the SPEC benchmarks is
detailed in:
<P>
[1] Alvin R. Lebeck and David A. Wood, "Cache Profiling and the SPEC
Benchmarks: A Case Study," IEEE Computer, vol. 27, no. 10, Oct. 1994,
pp. 15-26.

<P>
<H2> <A NAME="Tycho">Tycho and DineroIII:</A> </H2>
Tycho and dineroIII are uniprocessor cache simulators written by Mark
Hill. The simulators report the behavior of one or more alternative cache
designs in response to an input trace provided by the user (e.g., with
QPT). A trace is a list of the memory references that a program or
workload makes while it is executing. Both simulators are written in C,
use the same ASCII trace format, and have been distributed to dozens of
companies and universities.
<P>
The first simulator, tycho, simultaneously evaluates many alternative
uniprocessor caches, but severely restricts the design options that may be
varied [1]. Specifically, with one pass through an address trace, tycho
will produce a table of miss ratios for caches of many sizes and
associativities, provided that all caches have the same block (line) size,
do no prefetching, and use LRU replacement. Tycho is used, for example,
with the SPEC benchmark suite to examine numerous caches [2]. Tycho is
most useful for reducing the size of a large cache design space. A second
version of <EM>tycho</EM>--<EM>tychoII</EM>--provides higher performance
with the option of binary trace input and several other optimizations by
Madhusudhan Talluri. <EM>TychoII</EM>, however, is more complex than
<EM>tycho</EM> and has not been widely used.
<P>
The second simulator, dineroIII, evaluates only one uniprocessor cache at
a time, but produces more performance metrics (e.g., traffic to and from
memory) and allows more cache design options to be varied (e.g.,
write-back vs. write-through, LRU vs. random replacement, demand fetching
vs. prefetching). DineroIII is distributed for instructional use with a
popular graduate computer architecture textbook [3]. DineroIII is most
useful for carefully studying a few alternative cache designs.
<P>
[1] Mark D. Hill and Alan Jay Smith, "Evaluating Associativity in CPU
Caches," IEEE Trans. on Computers, C-38, 12, December 1989, p.1612-1630.
<P>
[2] Jeffrey D. Gee, Mark D. Hill, Dionisios N. Pnevmatikatos, Alan Jay
Smith, "Cache Performance of the SPEC Benchmark Suite," to appear, IEEE
Micro, August 1993, 3, 2.
<P>
[3] John L. Hennessy and David A. Patterson, Computer Architecture: A
Quantitative Approach, Morgan Kaufmann, San Mateo, California, 1990


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Last modified: May 14 1996 by James Larus
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  <!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><A HREF="http://www.cs.wisc.edu/~larus/larus.html">larus@cs.wisc.edu</A>
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